1. Future trends in microelectronics. 1. Technology innovation;Kim,2013
2. Assad-Eraghi F, Chen J, Solomon R, Chan T, Ko P, Hu C. Time dependence of fully-depleted SOI MOSFETs subthreshold current. In: Proceedings IEEE international SOI conference. Colorado; 1991. p. 32–3.
3. Okhonin S, Nagoga M, Sallese J, Fazan P. A SOI capacitor-less 1T-DRAM concept. In: Proceedings of the 2001 IEEE international SOI conference. Durango (USA); 2001. p. 153–4.
4. A capacitorless double-gate DRAM cell;Kuo;IEEE Electron Dev Lett,2002
5. Yoshida M, Tanaka T. A design of a capacitorless 1T-DRAM cell using gate-induced drain leakage (GIDL) current for low-power and high-speed embedded memory. In: IEDM technical digest; 2003. p. 37.6.1–4.