Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100K

Author:

Paz Bruna Cardoso,Cassé Mikaël,Barraud Sylvain,Reimbold Gilles,Vinet Maud,Faynot Olivier,Pavanello Marcelo Antonio

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference21 articles.

1. Multiple-gate SOI MOSFETs;Colinge;Solid-State Electron,2004

2. Strain-induced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10 nm width;Coquand;Symposium on VLSI technology (VLSIT),2012

3. Coquand R, Barraud S, Casse M, Leroux P, Vizioz C, Comboroure C, et al. Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10 nm width. In: 2012 13th International conference on ultimate integration on silicon (ULIS); 2012. p. 37–40.

4. High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling;Bangsaruntip;Electron devices meeting (IEDM), 2009 IEEE International,2009

5. Casse M, Barraud S, Le Royer C, Koyama M, Coquand R, Blachier D, et al. Study of piezoresistive properties of advanced CMOS transistors: thin film SOI, SiGe/SOI, unstrained and strained Tri-Gate nanowires. In: Electron devices meeting (IEDM), 2012 IEEE International; 2012. p. 28.1.1–4.

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