A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs-Reference-Cited by-同舟云学术

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A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs

Published:2014-06 Issue:3 Volume:47 Page:307-317
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Serafy Caleb,Shi Bing,Srivastava Ankur

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference12 articles.

1. C. Serafy, B. Shi, A. Srivastava, Geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs, in: Proceedings of the 23rd ACM International Conference on Great Lakes Symposium on VLSI, ACM, 2013, pp. 275–280.

2. G. Loh, 3D-stacked memory architectures for multi-core processors, in: 35th International Symposium on Computer Architecture, ISCA '08, 2008. doi: http://dx.doi.org/10.1109/ISCA.2008.15.

3. Y.-J. Lee, S. K. Lim, Timing analysis and optimization for 3D stacked multi-core microprocessors, in: 2010 IEEE International 3D Systems Integration Conference (3DIC), 2010. doi: http://dx.doi.org/10.1109/3DIC.2010.5751444.

4. J. Cho, E. Song, K. Yoon, J. Pak, W. Kim, J. H. Lee, et al., Modeling and analysis of through-silicon via (TSV) noise coupling and suppression using a guard ring, IEEE Trans. Compon. Packag. Manuf. Technol., 2011

5. C. Liu, T. Song, J. Cho, J. Kim, J. Kim, S. Lim, Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC, in: Proceedings of the 2011 48th Design Automation Conference, ACM, 2011.

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1. A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis;Applied Sciences;2023-07-18

2. CoSn3 Intermetallic Nanoparticles for Electronic Packaging;Nanomaterials;2022-11-20

3. TSV-Based 3-D ICs: Design Methods and Tools;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2017-10

4. NaPer: A TSV Noise-Aware Placer;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2017-05

5. References;Three-Dimensional Integrated Circuit Design;2017

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