Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies-Reference-Cited by-同舟云学术

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Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies

Published:2005-01 Issue:3 Volume:38 Page:491-504
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Chin Phillip,Zukowski Charles A.,Gristede George D.,Kosonocky Stephen V.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference23 articles.

1. Design challenges of technology scaling;Borkar;IEEE MICRO,1999

2. Int. Tech. Roadmap for Semiconductors (ITRS), http://public.itrs.net/, 2002.

3. A static power model for architects;Butts,2000

4. Impact of scaling on the effectiveness of dynamic power reduction schemes;Duarte,2002

5. Design techniques for gate-leakage reduction in CMOS circuits;Guindi,2003

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. LCNT-an approach to minimize leakage power in CMOS integrated circuits;Microsystem Technologies;2016-05-27

2. INDEP approach for leakage reduction in nanoscale CMOS circuits;International Journal of Electronics;2014-03-11

3. Using charge self-compensation domino full-adder with multiple supply and dual threshold voltage in 45nm technology;2009 10th International Conference on Ultimate Integration of Silicon;2009-03

4. Dual Threshold Domino OR Gates Leakage Power and Delay Forecasting Based on Wavelet Neural Networks in 45 nm Technology;2009 WRI Global Congress on Intelligent Systems;2009

5. Estimation for Speed and Leakage Power of Dual Threshold Domino OR Based on Wavelet Neural Networks;Advances in Neural Networks – ISNN 2009;2009

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