INDEP approach for leakage reduction in nanoscale CMOS circuits
Author:
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
http://www.tandfonline.com/doi/pdf/10.1080/00207217.2014.896042
Reference19 articles.
1. Leakage current reduction in CMOS VLSI circuits by input vector control
2. UDSM subthreshold leakage model for NMOS transistor stacks
3. Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits
4. Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies
5. EnhancedION/IOFFin ultra deep submicron CMOS devices using grooved nMOSFETs in comparison to planar nMOSFET
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