1. Chatterjee, B., Sachdev, M., Krishnnamurthy, R.: Designing Leakage Tolerant, Low Power Wide-OR Dominos for Sub-130 nm CMOS Technologies. Microelectronics Journal 36, 801–809 (2005)
2. Liu, Z., Kursun, V.: Leakage Power Characteristics of Dynamic Crcuits in Nanometer CMOS Technologies. IEEE Transactions on Circuits and Systems II 53, 692–696 (2006)
3. Guo, B.Z., Gong, N., Wang, J.H.: Designing Leakage-Tolerant and Noise-Immune Enhanced Low Power Wide OR Dominos in Sub-70nm CMOS Technologies. Chinese Journal of semiconductors 27, 804–811 (2006)
4. International Technology Roadmap for Semiconductors,
http://public.itrs.net/
5. Kuroda, T., Fujita, T., Mita, S., et al.: A 0.9 V 150 MHz 10 mW 4 mm2 2-D Discrete Cosine Transform Core Processor With Variable-Threshold-Voltage Scheme. In: 43rd IEEE International Solids-State Circuits Conference, pp. 1770–1779. IEEE Press, New York (1996)