Author:
da Costa E.,Monteiro J.,Bampi S.
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Reference39 articles.
1. E. Mussol, J. Cortadella, Low-power array multipliers with transition-retaining barriers, Proceedings of the PATMOS, 1995, pp. 227–235.
2. C. Wallace, A suggestion for a fast multiplier, IEEE Trans. Electron. Comput. (1964) 14–17.
3. H. Sam, A. Gupta, A generalized multibit recoding of two's complement binary numbers and its proof with application in multiplier implementations, IEEE Trans. Comput. (1990) 1006–1015.
4. K. Yano, et al., A 3.8-ns CMOS 16×16-b multiplier using complementary pass-transistor logic, IEEE J. Solid-State Circuits (1990) 388–395.
5. B. Millar, P. Madrid, E. Swartzlander, A fast hybrid multiplier combining booth and Wallace/DADDA algorithms, 35th Midwest Symposium on Circuits and Systems, 1992, pp. 158–165.
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