A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic-Reference-Cited by-同舟云学术

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A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic

Published:1990-04 Issue:2 Volume:25 Page:388-395
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Yano K.,Yamanaka T.,Nishida T.,Saito M.,Shimohigashi K.,Shimizu A.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx1/4/1876/00052161.pdf?arnumber=52161

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