Crosstalk-aware multi-bit flip-flop generation for power optimization-Reference-Cited by-同舟云学术

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Crosstalk-aware multi-bit flip-flop generation for power optimization

Published:2015-01 Issue: Volume:48 Page:146-157
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Hsu Chih-Cheng,Lin Mark Po-Hung,Chang Yao-Tsung

Funder

National Science Council (now Ministry of Science and Technology) of Taiwan

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference38 articles.

1. C.-C. Hsu, Y.-T. Chang, M.P.-H. Lin, Crosstalk-aware power optimization with multi-bit flip-flops, in: Proceedings of IEEE/ACM Asia South Pacific Design Automation Conference, 2012, pp. 431–436.

2. A. Krishnamoorthy, Minimize IC power without sacrificing performance, EE Times.

3. Power consumption estimation in CMOS VLSI chips;Liu;IEEE J. Solid-State Circuits,1994

4. J.G. Xi, W.-M. Dai, Buffer insertion and sizing under process variations for low power clock distribution, in: Proceedings of ACM/IEEE Design Automation Conference, 1995, pp. 491–496.

5. K. Wang, M. Marek-Sadowska, Buffer sizing for clock power minimization subject to general skew constraints, in: Proceedings of ACM/IEEE Design Automation Conference, 2004, pp. 159–164.

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2. Design Of Modified Data Driven Clock Gating And Look Ahead Clock Gating For Low Power;International Journal of Electrical and Electronics Research;2018-05-25

3. Minimizing detection-to-boosting latency toward low-power error-resilient circuits;Integration;2017-06

4. Probability-Driven Multibit Flip-Flop Integration With Clock Gating;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2017-03

5. A novel PDWC-UCO algorithm-based buffer placement in FPGA architecture;International Journal of Circuit Theory and Applications;2016-10-24

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