Author:
Xi Joe G.,Dai Wayne W. M.
Cited by
5 articles.
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1. A novel PDWC-UCO algorithm-based buffer placement in FPGA architecture;International Journal of Circuit Theory and Applications;2016-10-24
2. Clock Design and Synthesis;Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology;2016-04-14
3. Crosstalk-aware multi-bit flip-flop generation for power optimization;Integration;2015-01
4. Revisiting automated physical synthesis of high-performance clock networks;ACM Transactions on Design Automation of Electronic Systems;2013-03
5. Clock Skew Optimization for Peak Current Reduction;High Performance Clock Distribution Networks;1997