Probability-Driven Multibit Flip-Flop Integration With Clock Gating-Reference-Cited by-同舟云学术

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Probability-Driven Multibit Flip-Flop Integration With Clock Gating

Published:2017-03 Issue:3 Volume:25 Page:1173-1177
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Gluzer Doron,Wimer Shmuel^ORCID

Funder

Israel Chief Scientist’s Magnet Program, HiPer consortium

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/7862316/07589084.pdf?arnumber=7589084

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and analysis of low power high speed SBFF and MBFF for signal processing applications;e-Prime - Advances in Electrical Engineering, Electronics and Energy;2024-03

2. Power reduction using Unified techniques in Switch-tail Ring counter for sequential circuits;Analog Integrated Circuits and Signal Processing;2023-12-30

3. Machine Learning Based Flip-Flop Grouping for Toggling Driven Clock Gating;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21

4. A Timing Aware Connectivity Optimization Technique for Improving Energy Efficiency of High-Performance CPUs;2021 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS);2021-04-14

5. Converting Flip-Flop to Clock-Gated 3-Phase Latch-Based Designs using Graph-Based Retiming;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021

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