Author:
Wang Kai,Marek-Sadowska Malgorzata
Cited by
14 articles.
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1. Design & Benchmark of Single Bit & Multi Bit Sequential Elements in 65nm for Low Standby Power Consumption;2020 24th International Symposium on VLSI Design and Test (VDAT);2020-07
2. Latency constraint guided buffer sizing and layer assignment for clock trees with useful skew;Proceedings of the 24th Asia and South Pacific Design Automation Conference;2019-01-21
3. A novel PDWC-UCO algorithm-based buffer placement in FPGA architecture;International Journal of Circuit Theory and Applications;2016-10-24
4. Flip-flop clustering by weighted K-means algorithm;Proceedings of the 53rd Annual Design Automation Conference;2016-06-05
5. Clock Design and Synthesis;Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology;2016-04-14