Delay caused by resistive opens in interconnecting lines-Reference-Cited by-同舟云学术

Delay caused by resistive opens in interconnecting lines

Published:2009-06 Issue:3 Volume:42 Page:286-293
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Arumí D.,Rodríguez-Montañés R.,Figueras J.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference21 articles.

1. Topology dependence of floating gate faults in MOS integrated circuits;Renovell;Electronics Letters,1986

2. C.L. Henderson, J.M. Soden, C.F. Hawkins, The behavior and testing implications of CMOS IC open circuits, in: International Test Conference, 1991, pp. 302–303.

3. H. Sue, C. Di, J.A.G. Jess, Probability analysis for CMOS floating gate faults, in: Proceedings European Design and Test Conference, 1994, pp. 443–448.

4. Voltage and current-based fault simulation for interconnect open defects;Konuk;IEEE Transactions on Computed-Aided Design of Integrated Circuits and Systems,1999

5. Resistance characterization for weak open defects;Montañés;IEEE Design & Test of Computers,2002

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