Clock Faults Induced Min and Max Delay Violations
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
http://link.springer.com/content/pdf/10.1007/s10836-013-5426-4.pdf
Reference35 articles.
1. Arumi D, Rodriguez-Montanes R, Figueras J (2009) Delay caused by resistive opens in interconnecting lines. IEEE Integr VLSI J 42:286–293
2. Casimiro A et al (1993) “Experiments on Bridging Fault Analysis and Layout-Level DFT for CMOS Designs”, in Proc. of IEEE Defects and Fault Tolerance in VLSI Systems, pp. 109–116
3. Cheng SW, Chen H, Du C, Lim A (1994) The role of long and short paths in circuit performance optimization. IEEE Trans Comput-Aided Des Integr Circ Sys 13(7):857–864
4. Chung KY, Gupta SK, (2010) “Design and Test of Latch-Based Circuits to Maximize Performance, Yield, and Delay Test Quality”, in Proc. of IEEE Int’l Test Conf., pp. 1–10
5. Deleganes D, Douglas J, Kommandur B, Patyra M (2002) “Designing a 3GHz, 130 nm, Intel® Pentium® 4 Processor”, in Proc. of IEEE 2002 Symp. On VLSI Circuit, Dig. of Tech. Papers, pp. 130–133
1.学者识别学者识别
2.学术分析学术分析
3.人才评估人才评估
"同舟云学术"是以全球学者为主线，采集、加工和组织学术论文而形成的新型学术文献查询和分析系统，可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容，当前同舟云学术共收录了国内外主流学术期刊6万余种，收集的期刊论文及会议论文总量共计约1.5亿篇，并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询！咨询电话：010-8811{复制后删除}0370
www.globalauthorid.com
TOP
Copyright © 2019-2024 北京同舟云网络信息技术有限公司 京公网安备11010802033243号 京ICP备18003416号-3