Experiments on bridging fault analysis and layout-level DFT for CMOS designs-Reference-Cited by-同舟云学术

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Experiments on bridging fault analysis and layout-level DFT for CMOS designs

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Container-title:Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
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Author:

Casimiro A.,Simoes M.,Santos M.,Teixeira I.,Teixeira J.P.

Publisher

IEEE Comput. Soc. Press

Link

http://xplorestaging.ieee.org/ielx2/4647/13033/00595718.pdf?arnumber=595718

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Clock Faults Induced Min and Max Delay Violations;Journal of Electronic Testing;2013-12-15

2. Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2013-12

3. Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors;2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems;2009-10

4. Self-Checking Voter for High Speed TMR Systems;Journal of Electronic Testing;2005-08

5. On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;1997-07

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