A PVT aware differential delay circuit and its performance variation due to power supply noise

Author:

Tarafdar Anirban,Mondal Abir J.,Bera Uttam K.,Bhattacharyya B.K.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference22 articles.

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3. Matching properties of MOS transistor and delay line chains with self-aligned source/drain contacts;Bolt,1996

4. A VLSI array of low power spiking neurons and bistable synapses with spike timing dependent plasticity;Indiveri;IEEE Trans. Neural Network.,2006

5. A 10-GHz delay line frequency discriminator and PD/CP based CMOS phase noise measurement circuit;Hao;IEEE Trans. Microw. Theor. Tech.,2017

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