Effect of Power Supply Noise on Logical Reliability of MOS based Circuits-Reference-Cited by-同舟云学术

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Effect of Power Supply Noise on Logical Reliability of MOS based Circuits

Published:2023-01-05 Issue: Volume: Page:
ISSN:
Container-title:2023 Third International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT)
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Author:

Deb Debajit¹,Bhaumik Ghungur²,Chakraborty Udayan²

Affiliation:

1. Koneru Lakshmaiah Education Foundation,Department of ECE,Vaddeswaram,Andhra Pradesh,India,522302

2. Techno College of Engineering Agartala,Department of ECE,Agartala,Tripura,India,799004

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10117587/10117572/10118143.pdf?arnumber=10118143

Reference19 articles.

1. Power Supply Noise Rejection Improvement Method in Modern VLSI Design

2. On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits

3. Hightension power delivery: Operating 0.18 µm CMOS digital logic at 5.4 V;rajapandian;Proc Int Solid-State Circuits Conf,0

4. Raised cosine approximation signalling technique for reduced simultaneous switching noise

5. Power considerations in the design of the Alpha 21264 microprocessor

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. The effect of temperature on the electrical characteristics of zigzag and armchair black phosphorus based 2D MOSFET;Semiconductor Science and Technology;2024-09-12

2. A novel MTCMOS based 8T2M NVSRAM design for low power applications with high temperature endurance;Semiconductor Science and Technology;2024-07-19

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