On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits-Reference-Cited by-同舟云学术

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On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits

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Container-title:2005 Joint 30th International Conference on Infrared and Millimeter Waves and 13th International Conference on Terahertz Electronics
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Author:

Popovich M.,Friedman E.G.,Secareanu R.,Hartin O.L.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/10415/33077/01554517.pdf?arnumber=1554517

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Effect of Power Supply Noise on Logical Reliability of MOS based Circuits;2023 Third International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT);2023-01-05

2. Programming scheme based optimization of hybrid 4T-2R OxRAM NVSRAM;Semiconductor Science and Technology;2017-08-29

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