Design and Analysis of an Area and Power Efficient Programmable Delay Cell
Author:
Affiliation:
1. NIT Arunachal Pradesh,Electronics & Communication Engineering,Jote,India
2. CSIR - CEERI,Integrated Circuits & Systems Group,Pilani,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10483275/10483296/10483450.pdf?arnumber=10483450
Reference17 articles.
1. A VLSI Array of Low-Power Spiking Neurons and Bistable Synapses With Spike-Timing Dependent Plasticity
2. A 16 mW 250 ps Double-Hit-Resolution Input-Sampled Time-to-Digital Converter in 45-nm CMOS
3. A 1.0–4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control
4. A l00Ks/s 8.3ENOB l.7-time domain analog to digital converter;Kim;IEEE Trans. Circuits Syst. II Exp. Briefs,2014
5. A new linear delay element with self calibration
1.学者识别学者识别
2.学术分析学术分析
3.人才评估人才评估
"同舟云学术"是以全球学者为主线，采集、加工和组织学术论文而形成的新型学术文献查询和分析系统，可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容，当前同舟云学术共收录了国内外主流学术期刊6万余种，收集的期刊论文及会议论文总量共计约1.5亿篇，并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询！咨询电话：010-8811{复制后删除}0370
www.globalauthorid.com
TOP
Copyright © 2019-2024 北京同舟云网络信息技术有限公司 京公网安备11010802033243号 京ICP备18003416号-3