A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line-Reference-Cited by-同舟云学术

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A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line

Published:2000-02 Issue:2 Volume:35 Page:240-247
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Dudek P.,Szczepanski S.,Hatfield J.V.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/17827/00823449.pdf?arnumber=823449

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