Effect of trench depth and gate length shrinking assessment on the analog and linearity performance of TGRC-MOSFET-Reference-Cited by-同舟云学术

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Effect of trench depth and gate length shrinking assessment on the analog and linearity performance of TGRC-MOSFET

Published:2017-09 Issue: Volume:109 Page:626-640
ISSN:0749-6036
Container-title:Superlattices and Microstructures
language:en
Short-container-title:Superlattices and Microstructures

Author:

Kumar Ajay

Funder

Microelectronics Research Lab, Department of Engineering Physics and Electrical Engineering Department Delhi Technological University

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,General Materials Science

Reference32 articles.

1. RF Microelectronics;Razavi,1998

2. Roadmap for 22nm and beyond;Iwai;Microelectron. Eng.,2009

3. Analysis and modeling of dual-gate MOSFET’s;Barsan;Electron Devices IEEE Trans.,1981

4. Design guideline of an ultra-thin body SOI MOSFET for low-power and high-performance applications;An;Semicond. Sci. Technol.,2003

5. TCAD assessment of gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET and its multilayered gate architecture—part I: hot-carrier-reliability evaluation;Chaujar;Electron Devices IEEE Trans.,2008

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