Interface trap charge-based reliability assessment of high-k dielectric-modulated nanoscaled FD SOI MOSFET for low power digital ICs: Modeling and simulation-Reference-Cited by-同舟云学术

Interface trap charge-based reliability assessment of high-k dielectric-modulated nanoscaled FD SOI MOSFET for low power digital ICs: Modeling and simulation

Published:2021-06 Issue: Volume:154 Page:106871
ISSN:0749-6036
Container-title:Superlattices and Microstructures
language:en
Short-container-title:Superlattices and Microstructures

Author:

Srivastava Nilesh Anand^ORCID,Priya Anjali,Mishra Ram Awadh

Funder

Ministry of Electronics and Information technology

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,General Materials Science

Reference34 articles.

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3. Design of high speed and low-power ring oscillator circuit in recessed source/drain SOI technology;Priya;ECS Journal of Solid State Science and Technology,2019

4. Dual Metal Schottky Barrier Asymmetric Gate Stack Cylindrical Gate All Around (DM-SB-ASMGS-CGAA) MOSFET for Improved Analog Performance for High Frequency Application;Nandy,2019

5. Shallow Extension Engineered Dual Material Surrounding Gate (SEE-DM-SG) MOSFET for improved gate leakages, analysis of circuit and noise performance;Goel;AEU-International Journal of Electronics and Communications,2019

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