Performance optimization of nanoscale junctionless transistors through varying device design parameters for ultra-low power logic applications
Author:
Funder
University of Calcutta
Publisher
Elsevier BV
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,General Materials Science
Reference34 articles.
1. International Technology Roadmap for Semiconductors,2013
2. Ultra Low Power Junctionless MOSFETs for Subthreshold Logic Applications
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