Design and Optimization of Dual Material Gate Junctionless FinFET Using Dimensional Effect, Gate Oxide and Workfunction Engineering at 7 nm Technology Node
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-022-01769-6.pdf
Reference38 articles.
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3. Yan RH, Ourmazd A, Lee KF (1992) Scaling the Si MOSFET: from bulk to SOI to bulk. IEEE Trans Electron Devices 39:1704–1710. https://doi.org/10.1109/16.141237
4. Srivastava NA, Mishra K, Chauhan RK (n.d.) Analytical Modelling of Surface Potential of Modified Source FD-SOI MOSFET
5. Srivastava NA, Priya A, Mishra RA (2021) Interface trap charge-based reliability assessment of high-k dielectric-modulated nanoscaled FD SOI MOSFET for low power digital ICs: Modeling and simulation. Superlattice Microst 154:106871. https://doi.org/10.1016/j.spmi.2021.106871
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