Effects of high in-situ source/drain boron doping in p-FinFETs on physical and device performance characteristics-Reference-Cited by-同舟云学术

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Effects of high in-situ source/drain boron doping in p-FinFETs on physical and device performance characteristics

Published:2018-08 Issue: Volume:82 Page:9-13
ISSN:1369-8001
Container-title:Materials Science in Semiconductor Processing
language:en
Short-container-title:Materials Science in Semiconductor Processing

Author:

Shintri Shashidhar,Yong Chloe,Zhu Baofu,Byrappa Shayan,Fu Bianzhu,Lo Hsien-Ching,Choi Dongil,Kolagunta Venkat

Publisher

Elsevier BV

Subject

Mechanical Engineering,Mechanics of Materials,Condensed Matter Physics,General Materials Science

Reference13 articles.

1. Integration of highly-strained SiGe materials in 14 nm and beyond nodes FinFET technology;Wang;Solid-State Electron.,2015

2. M. Choi, V. Moroz, L. Smith, O. Penzin, "14 nm FinFET Stress Engineering with Epitaxial SiGe Source/Drain," Silicon-Germanium Technology and Device Meeting (ISTDM) International, Berkeley, CA, 2012, pp. 1–2. https://doi.org/10.1109/ISTDM.2012.6222469.

3. Comprehensive Evaluation and study of pattern dependency behavior in selective epitaxial growth of B-doped SiGe layers;Kolahdouz;IEEE Trans. Nanotechnol.,2009

4. Investigation of In situ boron-doping in SiGe source/drain layer growth for PMOS devices;Zhong;J. Nanomater.,2015

5. high quality SiGe:B of high Ge layer for 14nm and beyond FINFET processes;Liao;ECS Trans.,2013

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1. Efficient and accurate atomistic modeling of dopant migration using deep neural network;Materials Science in Semiconductor Processing;2022-06

2. Architecture and Optimization of 2T (Footprint) SRAM;IEEE Transactions on Electron Devices;2021-10

3. Abnormal Silicon-Germanium (SiGe) Epitaxial Growth in FinFETs;IEEE Transactions on Semiconductor Manufacturing;2020-05

4. Monolayer doping of silicon-germanium alloys: A balancing act between phosphorus incorporation and strain relaxation;Journal of Applied Physics;2019-07-14

5. Influence of SiGe on Parasitic Parameters in PMOS;2019 China Semiconductor Technology International Conference (CSTIC);2019-03

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