Automated high-level verification against clocked algorithmic specifications-Reference-Cited by-同舟云学术

Automated high-level verification against clocked algorithmic specifications

Published:1993 Issue: Volume: Page:147-154
ISSN:
Container-title:Computer Hardware Description Languages and their Applications
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Author:

Corella Francisco

Publisher

Elsevier

Reference11 articles.

1. J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill. Sequential circuit verification using symbolic model checking. In 27th Design Automation Conference, pages 46–51, 1990.

2. L. Claesen, F. Proesmans, E. Verlind, and H. De Man. SFG-Tracing: A methodology for the automatic verification of MOS transistor level implementations from high level behavioral specifications. In P. A. Subrahmanyam, editor, International Workshop on Formal Methods in VLSI Design, Miami, Florida, January 1991.

3. F. Corella, R. Camposano, R. Bergamaschi, and M. Payer. Verification of synchronous sequential circuits obtained from algorithmic specifications. In D. Borrione and R. Waxman, editors, Proceedings of the IFIP WG 10.2 Tenth International Symposium, Computer Hardware Description Languages and Their Applications, April 1991.

4. Francisco Corella. Automated verification of behavioral equivalence for microprocessors. To appear in IEEE Transactions on Computers. Available as IBM Technical Report RC 17751, revised January 1993.

5. Francisco Corella. Automated high-level verification against clocked algorithmic specifications. RC 18506, IBM Research, November 1992.

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