A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool
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Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/3-540-49519-3_15
Reference31 articles.
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3. Srinivas Devadas, Hi-Keung Tony Ma, Richard Newton, “On Verification of Sequential Machines at Differing Levels of Abstraction”, IEEE Transactions on Computer-Aided Design, June 1988.
4. Michael McFarland, “An Abstract Model of Behavior for Hardware Descriptions”, IEEE Transactions on Computers, July 1983.
5. F. Corella, R. Camposano, R. Bergamaschi, M. Payer, “Verification of Synchronous Sequential Circuits Obtained from Algorithmic Specifications,” Proc. Intl. Workshop on Formal Methods in VLSI Design, Miami, 1991.
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1. Towards Provably-Correct Hardware Compilation Tools Based on Pass Separation Techniques;Lecture Notes in Computer Science;2001
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