A low power and small area digital self-calibration technique for pipeline ADC
Author:
Publisher
Elsevier BV
Subject
Electrical and Electronic Engineering
Reference8 articles.
1. A background calibration in pipelined ADCs;Mafi;Int J Electron Commun,2013
2. A 14-bit 250 MS/s IF sampling pipelined ADC in 180 nm CMOS process;Zheng;IEEE Trans Circuits Syst I Regul Pap,2016
3. A 12 b 53 mW 195 MS/s pipeline ADC with 82 dB SFDR using split-ADC calibration;Sehgal;IEEE J Solid-State Circuits,2015
4. A self-calibrated pipeline ADC with 200 MHz IF-sampling frontend;Waltari;Analog Integr Circ Sig Process,2003
5. An integrator-based pipelined ADC with digital calibration;Wang;IEEE Trans Circuits Syst II Express Briefs,2015
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1. A new ripple carry adder structure based on a swing‐boosted full adder for concurrent error correction in low‐resolution pipeline analog‐to‐digital converters;International Journal of Circuit Theory and Applications;2024-02-13
2. Design of Different High-Speed Data Converters using Verilog;2022 International Conference on Knowledge Engineering and Communication Systems (ICKES);2022-12-28
3. A low‐power 10‐bit CCP‐based pipelined ADC using a multi‐level variable current source MDAC and an ultra‐low‐power double‐tail dynamic latch;International Journal of Circuit Theory and Applications;2021-01-19
4. Review: Parametric Variations in Analog-to-Digital Converters Using Different CMOS Technologies;Proceedings of International Conference on Communication and Artificial Intelligence;2021
5. Energy-efficient DAC switching technique for single-ended SAR ADCs;AEU - International Journal of Electronics and Communications;2020-09
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