A background calibration in pipelined ADCs

Author:

Mafi Hamid R.,Sodagar Amir M.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering

Reference19 articles.

1. A 10-bit 50-MS/s charge injection pipelined ADC using a novel digital calibration;Mafi,2012

2. A 10-bit 500-MS/s 55-mW CMOS ADC;Verma;IEEE J Solid State Circ,2009

3. Least mean square adaptive digital background calibration of pipelined analog-to-digital converters;Chiu;IEEE Trans Circ Syst I Regular Pap,2004

4. Background calibration of pipelined ADCs via decision boundary gap estimation;Brooks;IEEE Trans Circ Syst I Regular Pap,2008

5. A low-power capacitive charge pump based pipelined ADC;Ahmed;IEEE J Solid State Circ,2010

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1. Digital calibration of pipelined ADC using Newton–Raphson algorithm;Analog Integrated Circuits and Signal Processing;2020-05-08

2. Calibration of timing mismatch in TIADC based on monotonicity detecting of sampled data;IEICE Electronics Express;2020

3. A high accuracy current charge-pump based MDAC for pipelined ADCs;AEU - International Journal of Electronics and Communications;2019-03

4. A taxonomy of ADC architectures for ICT engineering curricula;AEU - International Journal of Electronics and Communications;2018-02

5. A low power and small area digital self-calibration technique for pipeline ADC;AEU - International Journal of Electronics and Communications;2018-01

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