Digital calibration of pipelined ADC using Newton–Raphson algorithm
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s10470-020-01659-0.pdf
Reference28 articles.
1. Jalali-Farahani, B., & Meruva, A. (2009). A 14-b 32 MS/s pipelined ADC with fast convergence comprehensive background calibration. Analog Integr Circuits Signal Process,61(1), 65–74.
2. Jia, H., & Lv, Y. (2016). A calibration technique based on sub-stages’ weights of pipelined ADC. Analog Integr Circuits Signal Process,89(1), 223–229.
3. Larsson, A., Silva-Martinez, J., & Soenen, E. (2014). A 360 fJ/conversion-step, 14-bit, 100 MS/s, digitally background calibrated pipelined ADC in 130-nm CMOS. Analog Integr Circuits Signal Process,81(1), 153–164.
4. Chen, Z.-H., Wu, H., Zhang, H., Wei, J.-H., Su, X., Xue, Y., et al. (2019). A 14-bit 250-MS/s charge-domain pipelined ADC with mix-signal foreground calibration. Analog Integr Circuits Signal Process,101(2), 283–295.
5. Li, J., & Moon, U.-K. (2003). Background calibration techniques for multistage pipelined ADCs with digital redundancy. IEEE Trans Circuits Syst II Analog Digital Signal Process,50(9), 531–538.
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1. New approach for digital calibration of pipelined analog to digital converters based on secant method;Integration;2022-01
2. A low‐power 10‐bit CCP‐based pipelined ADC using a multi‐level variable current source MDAC and an ultra‐low‐power double‐tail dynamic latch;International Journal of Circuit Theory and Applications;2021-01-19
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