A 360 fJ/conversion-step, 14-bit, 100 MS/s, digitally background calibrated pipelined ADC in 130-nm CMOS-Reference-Cited by-同舟云学术

A 360 fJ/conversion-step, 14-bit, 100 MS/s, digitally background calibrated pipelined ADC in 130-nm CMOS

Published:2014-08-17 Issue:1 Volume:81 Page:153-164
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Larsson A.,Silva-Martinez J.,Soenen E. G.

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-014-0376-z.pdf

Reference32 articles.

1. Dyer, K. C., Fu, D., Lewis, S. H., & Hurst, P. J. (1998). An analog background calibration technique for time-interleaved analog-to-digital converters. IEEE Journal of Solid-State Circuits, 33(12), 1912–1919.

2. Sonkusale, S. R., Van der Spiegel, J., Nagaraj, K. (2001). “Background digital error correction technique for pipelined analog-digital converters”, IEEE International Symposium on Circuits and Systems (pp. 408–411).

3. Gines, A. J., Peralias, E. J., Rueda, A. (2003). “Digital background calibration technique for pipeline ADCs with multi-bit stages”, IEEE International Symposium Circuits Systems (pp. 317–322).

4. Wang, X., Hurst, P. J., & Lewis, S. H. (2004). A 12-bit 20-Msample/s pipelined ADC with nested digital background calibration. IEEE Journal of Solid-State Circuits, 39(11), 1799–1808.

5. Eduri, U., Maloberti, F. (2004). “Online calibration of a Nyquist-rate ADC using output code-density histograms”, IEEE Transactions on Circuits System I, 51(1), 15–24.

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