A 12-bit 250 MS/s pipeline ADC with 78 dB SFDR in 0.13-µm CMOS
Author:
Affiliation:
1. National ASIC and System Engineering Centre, Southeast University, Nanjing, China
Funder
Scientific Research Foundation of Graduate School of Southeast University
National Natural Science Foundation of China
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
https://www.tandfonline.com/doi/pdf/10.1080/00207217.2018.1440426
Reference10 articles.
1. MOSFET-only pipelined analogue-to-digital converters: non-linearity compensation by digital calibration
2. A CMOS switch-capacitor 14-bit 100 Msps pipeline ADC with over 90 dB SFDR
3. A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter
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1. Highly-matched sub-ADC cells for pipeline analogue-to-digital converters;International Journal of Electronics;2019-06-09
2. A 25-GS/s 6-bit time-interleaved SAR ADC with design-for-test memory in 40-nm low-leakage CMOS;International Journal of Electronics;2019-02-06
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