High-sensitivity high-speed dynamic comparator with parallel input clocked switches-Reference-Cited by-同舟云学术

High-sensitivity high-speed dynamic comparator with parallel input clocked switches

Published:2020-07 Issue: Volume:122 Page:153236
ISSN:1434-8411
Container-title:AEU - International Journal of Electronics and Communications
language:en
Short-container-title:AEU - International Journal of Electronics and Communications

Author:

Zhang Xiaomeng,Li Shuo,Siferd Ray,Ren Saiyu

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering

Reference16 articles.

4. Hybrid latch-type tolerant sense amplifier for low-voltage SRAMs;Patel;IEEE Trans Circ Syst I,2019

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4. Design and Analysis of Enhanced Cascode Cross-Coupled Comparator;2024 International Conference on Smart Systems for applications in Electrical Sciences (ICSSES);2024-05-03

5. A Modified Single Tail Dynamic Latch Comparator with pMOS Switches for Low Power Applications;2024 1st International Conference on Trends in Engineering Systems and Technologies (ICTEST);2024-04-11