Design and Analysis of Enhanced Cascode Cross-Coupled Comparator-Reference-Cited by-同舟云学术

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Design and Analysis of Enhanced Cascode Cross-Coupled Comparator

Published:2024-05-03 Issue: Volume: Page:1-4
ISSN:
Container-title:2024 International Conference on Smart Systems for applications in Electrical Sciences (ICSSES)
language:
Short-container-title:

Author:

Gagana B L¹,Chetankumar Panwala Fenil²

Affiliation:

1. Siddaganga Institute Of Technology,M.Tech in VLSI Design and Embedded systems,Dept of Electronics & Instrumentation Engineering,Tumkur,India,572103

2. Siddaganga Institute Of Technology,Dept of Electronics & Instrumentation Engineering,Tumkur,India,572103

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10560480/10561248/10561347.pdf?arnumber=10561347

Reference15 articles.

1. A 12-bit 200MS/s pipeline ADC with 91 mW power and 66 dB SNDR

2. A 2.6 b/cycle-architecture-based 10 b 1.7 GS/s 15.4 mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique;Hong

3. A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology

4. A Low-Power Low-Noise Dynamic Comparator With Latch-Embedding Floating Amplifier

5. A Low-Power High-Speed Comparator for Precise Applications

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