A 12-bit 200MS/s pipeline ADC with 91 mW power and 66 dB SNDR
Author:
Funder
National Natural Science Foundation of China
Publisher
Elsevier BV
Subject
General Engineering
Reference16 articles.
1. A 12b 250 MS/s Pipelined ADC With Virtual ground reference buffers;Boo;IEEE J. Solid-State Circuits,2015
2. A 12 bit 200MS/s zero-crossing-based Pipelined ADC With early sub-ADC decision and output residue background calibration;Soon-Kyun Shin;IEEE J. Solid-State Circuits,2014
3. A 16-bit, 125MS/s, 385 mW, 78.7 dB SNR CMOS pipeline ADC;Devarajan;IEEE J. Solid-State Circuits,2009
4. A 16-bit 250-MS/s IF sampling Pipelined ADC With background calibration;Ali;IEEE J. Solid-State Circuits,2010
5. A 10-bit 200-MS/s zero-crossing-based pipeline ADC in 0.13-μm CMOS technology;Chu;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2015
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