A novel open-loop high-speed CMOS sample-and-hold-Reference-Cited by-同舟云学术

A novel open-loop high-speed CMOS sample-and-hold

Published:2008-09 Issue:8 Volume:62 Page:588-596
ISSN:1434-8411
Container-title:AEU - International Journal of Electronics and Communications
language:en
Short-container-title:AEU - International Journal of Electronics and Communications

Author:

Mousazadeh Morteza,Hadidi Khayrollah,Khoei Abdollah

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering

Reference6 articles.

1. Hadidi K. Data converters’ course notes. Urmia University, Urmia, Iran, 2005.

2. Jewett R, Corcoran J. Steinbach G. A 12b 20ms/sec ripple-through adc. ISSCC digest of Technical Paper, 1999, pp. 34–5.

3. Hadidi K, Muramatsu D, Oue T, Matsumoto T. A 500ms/sec −54db thd s/h circuit in a 0.5μm cmos process. 25th European solid–state circuits conference, Duisburg, Germany, 1999, pp. 158–61.

4. Hadidi K, Sobhi J, Hasankhan A, Muramatsu D, Matsumoto T. A novel highly linear cmos buffer. The 5th IEEE international conference on electronics, circuit and systems, Lisbon, Portugal, 1998, pp. 369–71.

5. Principles of data conversion system design;Razavi,1995

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