An energy-efficient sample-and-hold circuit in CNTFET technology for high-speed applications
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/content/pdf/10.1007/s10470-020-01607-y.pdf
Reference32 articles.
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4. Waltari, M., & Hulonen, K. (1998). A 10-bit 220-MSample/s CMOS sample-and-hold circuit. ISCAS‘98. In Proceedings of the 1998 IEEE international symposium on circuits and systems (pp. 253–256).
5. Mousazadeh, M. (2017). A highly linear open-loop high-speed CMOS sample-and-hold. Analog Integrated Circuits and Signal Processing,90(3), 703–710.
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