A broadband DC-coupling 16 GS/s sample-and-hold amplifier in 0.13 μm SiGe BiCMOS process

Author:

Ding Hao,Wang Jian-ye,Cheng Xu,Wang Dong

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering

Reference44 articles.

1. A 64Gb/s PAM-4 transceiver utilizing an adaptive threshold ADC in 16nm FinFET;Wang,2018

2. Seng-Pan U. A 16-mW 1-GS/s with 49.6-dB SNDR TI-SAR ADC for software-defined radio in 65-nm CMOS;Qiu;IEEE Trans on Very Large Scale Integration (VLSI) Systems,2018

3. A 2-GS/s 8-bit time-interleaved SAR ADC for millimeter-wave pulsed radar baseband SoC;Miki;IEEE J Solid-State Circuits,2017

4. A fully passive compressive sensing SAR ADC for low-power wireless sensors;Guo;IEEE J Solid-State Circuits,2017

5. A 5-bit 1.8 GS/s ADC-based receiver with twotap low-overhead embedded DFE in 130-nm CMOS.;Mahmoudi;AEU-Int J Electron Commun,2018

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