A 5-bit 1.8 GS/s ADC-based receiver with two-tap low-overhead embedded DFE in 130-nm CMOS
Author:
Publisher
Elsevier BV
Subject
Electrical and Electronic Engineering
Reference35 articles.
1. A 90 nm CMOS DSP MLSD transceiver with integrated AFE for electronic dispersion compensation of multimode optical fibers at 10 Gb/s;Agazzi;IEEE J Solid-State Circuits,2008
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3. A 500 mW ADC-based CMOS AFE with digital calibration for 10 gb/s serial links over kr-backplane and multimode fiber;Cao;IEEE J Solid-State Circuits,2010
4. A 32 Gb/s data-interpolator receiver with two-tap DFE fabricated with 28-nm CMOS process;Doi;IEEE J Solid-State Circuits,2013
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3. A 6-Bit 1.5-GS/s SAR ADC With Smart Speculative Two-Tap Embedded DFE in 130-nm CMOS for Wireline Receiver Applications;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-05
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5. Calibration of timing mismatch in TIADC based on monotonicity detecting of sampled data;IEICE Electronics Express;2020
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