A 70-MS/s Vcm-free 10-bit-resolution SAR ADC with a novel DAC structure to reduce area andparasitic capacitance effect-Reference-Cited by-同舟云学术

A 70-MS/s Vcm-free 10-bit-resolution SAR ADC with a novel DAC structure to reduce area andparasitic capacitance effect

Published:2022-07 Issue: Volume:152 Page:154256
ISSN:1434-8411
Container-title:AEU - International Journal of Electronics and Communications
language:en
Short-container-title:AEU - International Journal of Electronics and Communications

Author:

Aghdami Majid Vatan Parast,Mousazadeh Morteza,Sobhi Jafar,Kouzekonani Ziaddin Daei

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering

Reference20 articles.

1. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure;Liu;IEEE J Solid-State Circ,2010

2. A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS;Zhu;IEEE J Solid-State Circ,2010

3. A 10-bit 50-MS/s redundant SAR ADC with split capacitive-array DAC;Arian;Analog Int Circ Sig Process,2012

4. Guo W, Mirabbasi S. A low-power 10-bit 50-MS/s SAR ADC using a parasitic-compensated split-capacitor DAC. In: 2012 IEEE international symposium on circuits and systems (ISCAS). IEEE; 2012 May 20. p. 1275–8.

5. A 9-bit 80 MS/s successive approximation register analog-to-digital converter with a capacitor reduction technique;Cho;IEEE Trans Circ Syst II Exp Briefs,2010

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