1. Liu, C.–C., Chang, S.-J., Huang, G.-Y., & Lin, Y.-Z. (2010). A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure. IEEE Journal of Solid-State Circuits, 45(4), 731–740.
2. Cho, S.-H., Lee, C.-K., Kwon, J.-K., & Ryu, S.-T. (2011). A 550-uW 10-bit 40-MS/s SAR ADC with multistep addition-only digital error correction. IEEE Journal of Solid-State Circuits, 46(8), 1881–1892.
3. Zhu, Y., Chan, C.-H., Chio, U.-F., Sin, S.-W., U, S.-P., Martins, R.-P., et al. (2010). A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS. IEEE Journal of Solid-State Circuits, 45(5), 1111–1121.
4. Liu, C.-C., Chang, S.-J., Huang, G.-Y., Lin, Y.-Z., Huang, C.-M., Huang, C.-H., Bu, L., & Tsai, C.-C. (2010). A 10 b 100MS/s 1.13 mW SAR ADC with binary-scaled error compensation. In Proceedings of IEEE ISSCC Digest of Technical Papers (pp. 386–387). San Francisco.
5. Kuttner, F. (2002). A 1.2 V 10 b 20 M sample/s non-binary successive approximation ADC in 0.13 μm CMOS. In Proceedings of IEEE ISSCC (pp. 176–177). San Francisco.