A low-power 10-bit 50-MS/s SAR ADC using a parasitic-compensated split-capacitor DAC-Reference-Cited by-同舟云学术

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A low-power 10-bit 50-MS/s SAR ADC using a parasitic-compensated split-capacitor DAC

Published:2012-05 Issue: Volume: Page:
ISSN:
Container-title:2012 IEEE International Symposium on Circuits and Systems
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Author:

Guo Wei,Mirabbasi Shahriar

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6257548/6270389/06271470.pdf?arnumber=6271470

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 10-bit 45.5Ms/s SAR ADC based on Multi-Segmentation Split-Capacitive DAC;2023 International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan);2023-07-17

2. A 2.71 fJ/conversion-step 10-bit 50 MSPS split-capacitor array SAR ADC for FOG systems;International Journal of Electronics;2022-09-22

3. A 70-MS/s Vcm-free 10-bit-resolution SAR ADC with a novel DAC structure to reduce area andparasitic capacitance effect;AEU - International Journal of Electronics and Communications;2022-07

4. Fast front-end electronics for semiconductor tracking detectors: Trends and perspectives;Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment;2014-11

5. A cryogenic 10-bit successive approximation register analog-to-digital converter design with modified device model;Journal of Shanghai Jiaotong University (Science);2013-10

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