On-chip weak resistive defect diagnosis with performance enhancement in 45 nm technology static random access memory

Author:

Barekar SheetalORCID,Mali Madan

Publisher

Elsevier BV

Subject

General Engineering

Reference21 articles.

1. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test;Pavlov,2008

2. Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations;Chen;IEEE Trans. Very Large Scale Integr. Syst.,2005

3. Resistive-open defects in embedded-SRAM core cells: analysis and march test solution;Dilillo;Proc. - Asian Test. Symp.,2004

4. Study of read recovery dynamic faults in 6T SRAMS and method to improve test time;Dubey;J. Electron. Test. Theory Appl.,2010

5. Analysis of dynamic faults in embedded-SRAMs: implications for memory test;Borri;J. Electron. Test. Theory Appl.,2005

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