A novel indirect read technique based SRAM with ability to charge recycle and differential read for low power consumption, high stability and performance

Author:

Nayak Debasish,Rout Prakash Kumar,Sahu Sudhakar,Acharya Debiprasad Priyabrata,Nanda Umakanta,Tripthy Dhananjaya

Publisher

Elsevier BV

Subject

General Engineering

Reference27 articles.

1. Current starving the SRAM Cell: a strategy to improve cell stability and power;Nayak;Circ. Syst. Signal Process.,2017

2. A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy, IEEE;Verma;J. Solid-State Circuits,2008

3. Characterization of a novel nine transistor SRAM cell;Liu;IEEE Trans. Very Large Scale Integr. Syst.,2008

4. A highly-stable nanometer memory for low-power design;Lin,2008

5. A double pumped single-line-cache SRAM architecture for ultra-low energy IoT and machine learning applications;Banerjee,2019

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2. A novel CNTFET based Schmitt-Trigger read decoupled 12T SRAM cell with high speed, low power, and high Ion/Ioff ratio;AEU - International Journal of Electronics and Communications;2023-07

3. CNTFET-based Data Independent Power Efficient and Robust 8T SRAM Cell;ECS Journal of Solid State Science and Technology;2023-06-01

4. A Low Power Feedback Cutting 8T SRAM Cell for Improved Stability;2023 International Conference on Device Intelligence, Computing and Communication Technologies, (DICCT);2023-03-17

5. An offset cancellation technique for SRAM sense amplifier based on relation of the delay and offset;Microelectronics Journal;2022-10

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