Current Starving the SRAM Cell: A Strategy to Improve Cell Stability and Power-Reference-Cited by-同舟云学术

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Current Starving the SRAM Cell: A Strategy to Improve Cell Stability and Power

Published:2016-12-03 Issue:8 Volume:36 Page:3047-3070
ISSN:0278-081X
Container-title:Circuits, Systems, and Signal Processing
language:en
Short-container-title:Circuits Syst Signal Process

Author:

Nayak Debasish,Acharya Debiprasad Priyabrata,Mahapatra Kamalakanta

Publisher

Springer Science and Business Media LLC

Subject

Applied Mathematics,Signal Processing

Link

http://link.springer.com/article/10.1007/s00034-016-0466-5/fulltext.html

Reference25 articles.

1. B. Alorda, G. Torrens, S. Bota et al., Adaptive static and dynamic noise margin improvement in minimum-sized 6T-SRAM cells. Microelectron. Reliab. 54(11), 2613–2620 (2014)

2. A. Bansal, R. Rao, J.J. Kim, S. Zafar et al., Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability. Microelectron. Reliab. 49(6), 642–649 (2009)

3. P. Elakkumanan, C. Thondapu, R. Sridhar, A gate leakage reduction strategy for sub-70 nm memory circuits, in Proceedings of IEEE workshop on Implementation of High Performance Circuits (DCAS-04, 2004), pp. 145-148

4. E. Grossar, M. Stucchi, K. Maex et al., Read stability and write ability analysis of SRAM cells for nanometer technologies. IEEE J. Solid State Circuits 41(11), 2577–2588 (2006)

5. S. Hanson, M. Seok, Y.-S. Lin et al., A low-voltage processor for sensing applications with picowatt standby mode. IEEE J. Solid State Circuits 44(4), 1145–1155 (2009)

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1. Power Efficient Hybrid Low-Power Technique for an SRAM cell;2024 IEEE 4th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA);2024-05-17

2. 10T SRAM cell Analysis for improved Read and Write Noise Margin;2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT);2023-07-06

3. CNTFET-based Data Independent Power Efficient and Robust 8T SRAM Cell;ECS Journal of Solid State Science and Technology;2023-06-01

4. Design and performance improvement of low power SRAM using deep submicron technology;Analog Integrated Circuits and Signal Processing;2022-11-12

5. Design and comparative analysis of SRAM array using low leakage controlled transistor technique with improved delay;Journal of Ambient Intelligence and Humanized Computing;2021-06-29

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