Adaptive static and dynamic noise margin improvement in minimum-sized 6T-SRAM cells

Author:

Alorda Bartomeu,Torrens Gabriel,Bota Sebastia,Segura Jaume

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference27 articles.

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2. The impact of random device variation on SRAM Cell stability in sub-90-nm CMOS Technologies;Agarwal;IEEE Trans Very Large Scale Integr (VLSI) Syst,2008

3. 0.248μm2 and 0.334μm2 conventional bulk 6T-SRAM bit-cells for 45nm node low cost – general purpose applications;Boeuf;VLSI Technol,2005

4. Wu SW et al. A highly manufacturable 28nm CMOS low power platform technology with fully functional 64Mb SRAM using dual/tripe gate oxide process. VLSI Technology. In: 2009 Symposium on, p. 210–211.

5. Static noise margin variation for sub-threshold SRAM in 65-nm CMOS;Calhoun;IEEE J Solid-State Circ,2006

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4. Systematic Transistor Sizing of a CNFET-Based Ternary Inverter for High Performance and Noise Margin Enlargement;IEEE Access;2022

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