Systematic Transistor Sizing of a CNFET-Based Ternary Inverter for High Performance and Noise Margin Enlargement-Reference-Cited by-同舟云学术

Systematic Transistor Sizing of a CNFET-Based Ternary Inverter for High Performance and Noise Margin Enlargement

Published:2022 Issue: Volume:10 Page:10553-10565
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Takbiri Mehdi,Navi Keivan^ORCID,Mirzaee Reza Faghih^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science

Link

http://xplorestaging.ieee.org/ielx7/6287639/9668973/09687537.pdf?arnumber=9687537

Reference56 articles.

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5. Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits

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