Author:
Demartinos Andreas C.,Tsimpos Andreas,Vlassis Spyridon,Souliotis George,Sgourenas Savvas
Funder
Andreas Mentzelopoulos Scholarships of the University of Patras
Reference24 articles.
1. A 90-nm CMOS 5-GHz ring-oscillator PLL with delay-discriminator-based active phase-noise cancellation;Min;IEEE J. Solid-State Circuits,2013
2. Low-spur, low-phase-noise clock multiplier based on a combination of PLL and recirculating DLL with dual-pulse ring oscillator and self-correcting charge pump;Gierkink;IEEE J. Solid-State Circuits,2008
3. A 2.5Gb/s run-length-tolerant burst-mode CDR based on a 1/8th-rate dual pulse ring oscillator;Gierkink;IEEE J. Solid-State Circuits,2008
4. A wide-tuning range 1.8GHz quadrature VCO utilizing coupled ring oscillators;Mesgarzadeh;IEEE Int. Symp. Circuits Syst.,2006
5. A multi-phase multi-frequency clock generator using superharmonic injection locked multipath ring oscillators as frequency dividers;Hafez;IEEE Asian Solid State Circuits Conf.,2012
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