1. B.A. Abderazek, Dynamic instructions issue algorithm and a queue execution model toward the design of hybrid processor architecture, Ph.D. Thesis, Graduate School of Information Systems, the University of Electro-Communications, 2002.
2. B.A. Abderazek, S. Shigeta, T. Yoshinaga, M. Sowa, Reduced bit-width instruction set architecture for Q-mode execution in hybrid processor architecture, in: IPSJ, Information Processing Society of Japan, June 2003, pp. 19–23.
3. B.A. Abderazek, M. Arsenji, S. Shigeta, T. Yoshinaga, M. Sowa, Queue processor for novel queue computing paradigm based on produced order scheme, in: HPC2004, International Conference on High Performance Computing, Tokyo, July 2004, pp. 169–177.
4. B.A. Abderazek, S. Kawata, T. Yoshinaga, M. Sowa, Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core, in: EUC 2005, The 2005 IFIP International Conference on Embedded and Ubiquitous Computing, Nagasaki, Japan, December 6–9, 2005, pp. 340–349.
5. High-level modeling and FPGA prototyping of produced order parallel queue processor core;Abderazek;J. Supercomputing,2006