Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture

Author:

Abderazek Ben Abdallah,Masuda Masashi,Canedo Arquimedes,Kuroda Kenichi

Publisher

Springer Science and Business Media LLC

Subject

Hardware and Architecture,Information Systems,Theoretical Computer Science,Software

Reference36 articles.

1. Abderazek BA, Kawata S, Sowa M (2006) Design and architecture for an embedded 32-bit QueueCore. J Embed Comput 2(2):191–205

2. Abderazek BA, Yoshinaga T, Sowa M (2006) High-level modeling and FPGA prototyping of produced order parallel queue processor core. J Supercomput 38(1):3–15

3. Abderazek BA, Canedo A, Yoshinga T, Sowa M (2008) The QC-2 parallel queue processor architecture. J Parallel Distrib Comput 68(2):235–245

4. Aho AV, Sethi R, Ullman JD (1986) Compilers principles, techniques, and tools. Addison-Wesley, Reading

5. Allen R, Kennedy K (2002) Optimizing compilers for modern architectures. Morgan Kaufman, San Mateo

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